1. Field of the Invention
The present invention relates to a small-sized semiconductor device typified by CSP (Chip Size Package) and to a method for fabricating the same.
This application is counterpart of Japanese patent application, Serial Number 138584/2003, filed May 16, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Traditionally, in integrated circuit packages having semiconductor devices such as semiconductor integrated circuits packaged, a demand for the realization of reduction in size and in thickness is increasing. In recent years, with a focus on the semiconductor integrated circuit package in the field for which the reduction in thickness is demanded particularly, CSP is proposed in which ball-shaped terminals are arranged on the surface of a semiconductor device in a grid shape.
For example, the CSP is fabricated as shown in FIGS. 11A to 11D. Fist, a wafer 52 formed with devices to be semiconductor chips 50 is prepared, and an insulating film 53 such as polyimide is formed on the front side thereof (FIG. 11A). Then, a redistribution wiring layer 54 and posts 56 are formed on the front side of the insulating film 53 so as to be electrically connected to terminals of integrated circuits of the devices, not shown (FIG. 11B). Subsequently, after the entire front side is covered with an encapsulating resin 58 (FIG. 11C), the surfaces of the posts 58 are exposed by cutting, solder balls 60 are formed on the surfaces of the exposed posts 56, and the wafer is separated into individual pieces to complete semiconductor devices (FIG. 11D).
Furthermore, in these days, it is proposed that such the CSP undergoes three-dimensional packaging (stack mounting). For example, it is proposed in JP-A-6-5665 and JP-A-2000-243900 that semiconductor chips are stacked through a conductive member formed on the side wall of the semiconductor chips. In this proposal, through holes are disposed on scribing lines of a wafer formed with devices to be the semiconductor chips, and the conductive member is formed on the inner wall of the through holes.
In addition, it is proposed in JP-A-2002-93942 that a wiring layer (conductive member) is formed from the front side through the side to the back side of a semiconductor chip, external terminals are disposed on the front and back sides of the semiconductor chip, and a plurality of the semiconductor chips is stacked through the external terminals. In this proposal, a trench (groove) is formed by controlling the depth to reach from the back side of a wafer formed with devices to be the semiconductor chips to a redistribution wiring portion formed on the front side, an insulating material (resin) is filed in the groove to form through holes in the insulating material, and a conductive member is formed on the inner wall thereof.
[Patent Document 1]
JP-A-6-5665
[Patent Document 2]
JP-A-2000-243900
[Patent Document 3]
JP-A-2002-93942